| Device Utilization Summary | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
30,064 |
184,304 |
16% |
|
| Number used as Flip Flops |
30,064 |
|
|
|
| Number used as Latches |
0 |
|
|
|
| Number used as Latch-thrus |
0 |
|
|
|
| Number used as AND/OR logics |
0 |
|
|
|
| Number of Slice LUTs |
51,258 |
92,152 |
55% |
|
| Number used as logic |
44,294 |
92,152 |
48% |
|
| Number using O6 output only |
34,146 |
|
|
|
| Number using O5 output only |
1,298 |
|
|
|
| Number using O5 and O6 |
8,850 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
6,101 |
21,680 |
28% |
|
| Number used as Dual Port RAM |
3,598 |
|
|
|
| Number using O6 output only |
1,010 |
|
|
|
| Number using O5 output only |
44 |
|
|
|
| Number using O5 and O6 |
2,544 |
|
|
|
| Number used as Single Port RAM |
2,502 |
|
|
|
| Number using O6 output only |
17 |
|
|
|
| Number using O5 output only |
3 |
|
|
|
| Number using O5 and O6 |
2,482 |
|
|
|
| Number used as Shift Register |
1 |
|
|
|
| Number using O6 output only |
1 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
0 |
|
|
|
| Number used exclusively as route-thrus |
863 |
|
|
|
| Number with same-slice register load |
713 |
|
|
|
| Number with same-slice carry load |
150 |
|
|
|
| Number with other load |
0 |
|
|
|
| Number of occupied Slices |
17,232 |
23,038 |
74% |
|
| Number of MUXCYs used |
12,600 |
46,076 |
27% |
|
| Number of LUT Flip Flop pairs used |
57,302 |
|
|
|
| Number with an unused Flip Flop |
29,599 |
57,302 |
51% |
|
| Number with an unused LUT |
6,044 |
57,302 |
10% |
|
| Number of fully used LUT-FF pairs |
21,659 |
57,302 |
37% |
|
| Number of unique control sets |
2,967 |
|
|
|
Number of slice register sites lost
to control set restrictions |
10,209 |
184,304 |
5% |
|
| Number of bonded IOBs |
44 |
338 |
13% |
|
| Number of LOCed IOBs |
44 |
44 |
100% |
|
| IOB Flip Flops |
58 |
|
|
|
| Number of RAMB16BWERs |
10 |
268 |
3% |
|
| Number of RAMB8BWERs |
497 |
536 |
92% |
|
| Number of BUFIO2/BUFIO2_2CLKs |
1 |
32 |
3% |
|
| Number used as BUFIO2s |
1 |
|
|
|
| Number used as BUFIO2_2CLKs |
0 |
|
|
|
| Number of BUFIO2FB/BUFIO2FB_2CLKs |
1 |
32 |
3% |
|
| Number used as BUFIO2FBs |
1 |
|
|
|
| Number used as BUFIO2FB_2CLKs |
0 |
|
|
|
| Number of BUFG/BUFGMUXs |
3 |
16 |
18% |
|
| Number used as BUFGs |
2 |
|
|
|
| Number used as BUFGMUX |
1 |
|
|
|
| Number of DCM/DCM_CLKGENs |
2 |
12 |
16% |
|
| Number used as DCMs |
1 |
|
|
|
| Number used as DCM_CLKGENs |
1 |
|
|
|
| Number of ILOGIC2/ISERDES2s |
20 |
586 |
3% |
|
| Number used as ILOGIC2s |
20 |
|
|
|
| Number used as ISERDES2s |
0 |
|
|
|
| Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
586 |
0% |
|
| Number of OLOGIC2/OSERDES2s |
22 |
586 |
3% |
|
| Number used as OLOGIC2s |
22 |
|
|
|
| Number used as OSERDES2s |
0 |
|
|
|
| Number of BSCANs |
0 |
4 |
0% |
|
| Number of BUFHs |
0 |
384 |
0% |
|
| Number of BUFPLLs |
0 |
8 |
0% |
|
| Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
| Number of DSP48A1s |
1 |
180 |
1% |
|
| Number of ICAPs |
0 |
1 |
0% |
|
| Number of MCBs |
0 |
4 |
0% |
|
| Number of PCILOGICSEs |
0 |
2 |
0% |
|
| Number of PLL_ADVs |
1 |
6 |
16% |
|
| Number of LOCed PLL_ADVs |
1 |
1 |
100% |
|
| Number of PMVs |
0 |
1 |
0% |
|
| Number of STARTUPs |
1 |
1 |
100% |
|
| Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
| Average Fanout of Non-Clock Nets |
3.61 |
|
|
|